1. Field of the Invention
This invention generally relates to semiconductor memory devices and in particular to redundant memory cells used to maintain semiconductor memory cell operation despite the occurrence of defects in the semiconductor.
2. Description of the Related Art
In general, to access the magnitude of reliability degradation in semiconductor memory devices caused by, for example, manufacturing or assembly errors, factory screening is normally performed to determine the device's effectiveness or ability to perform its function. If a defective cell is found during screening operations, the defective cell is blinded, and a redundant cell provided in the semiconductor memory is used instead of the defective cell. In particular, data access to the cell determined to be defective is switched to that of the redundant cell in order to maintain device operability.
The process by which data access is switched from the defective to redundant cell is performed by disconnecting redundant fuses in a redundant circuit incorporated on the semiconductor chip. When the memory device receives an address signal to select a defective cell, the redundant cell is selected in place of the defective cell in response to the address signal. After the remedial process of replacing the defective cell with the redundant cell as described above, semiconductor memory chips are subjected to a packaging process.
Unfortunately, even after these redundancy detection and switching operations, some semiconductor memory devices are subject to device degradation. Oftentimes, therefore, semiconductor memory device manufacturers generally undertake an analysis as to whether the defective operation of the device is caused by the replaced redundant cell or by circuit elements other than the redundant cell. To do this, the address of the redundant cell i.e., the address of the defective cell, must be known. In order to enable the detection of the redundant cell address, conventional semiconductor memory chips utilize a signature circuit formed on the semiconductor chip.
FIG. 1 shows one example of a signature circuit used in a conventional semiconductor memory device. The signature circuit 1 includes an address signal comparator 2. The address signal comparator 2 receives address signals A.sub.0 to A.sub.n from an external unit such as a CPU or the like, as well as redundant address signals AJ.sub.O to AJ.sub.n from a redundant address setter (not shown). The address signal comparator 2 compares the addresses A.sub.O to A.sub.n with the redundant addresses AJ.sub.O to AJ.sub.n, and outputs a high level signal when the compared addresses coincide with each other. The output signal of the address signal comparator 2 is input via a first N-channel MOS transistor Tr1 to the gate of a second N-channel MOS transistor Tr2. The first transistor Tr1 has a gate connected to a power source Vcc, allowing the transistor Tr1 to be maintained on at all times. The second transistor Tr2 has a source connected to the power source Vcc and a drain connected to a measuring terminal 3 via two N-channel MOS transistors Tr3 and Tr4. Each of the third and fourth transistors Tr3 and Tr4 has a gate connected to the measuring terminal 3. A capacitor C is provided between the gate of the second transistor Tr2 and the measuring terminal 3. The measuring terminal 3 is connected to a tester 7 to check the operation of a memory device.
The operation of the signature circuit 1 will now be described. The measuring terminal 3 is supplied with a measuring voltage VE from the tester 7 every time the address signals A.sub.0 to A.sub.n and the redundant address signals AJ.sub.O to AJ.sub.n are input to the address signal comparator 2. The measuring voltage VE is set higher than Vcc plus 3 V.sub.th, where "V.sub.th " is the threshold value of each of the transistors Tr2 to tr4. If the address signals A.sub.O to A.sub.n do not coincide with the redundant address signals AJ.sub.O to AJ.sub.n, the address signal comparator 2 outputs a low level signal, setting the gate potential of the transistor Tr2 low and turning the transistor Tr2 off. When the measuring voltage VE is applied to the measuring terminal 3, the transistors Tr3 and Tr4 turn on. However, the transistor Tr2 is kept off, so that no current flows from the tester 7 to the measuring terminal 3.
When the address signals A.sub.O to A.sub.n coincide with the redundant address signals AJ.sub.O to AJ.sub.n, the address signal comparator 2 outputs an high level signal. At this time, the gate of the transistor Tr2 goes high, however, the transistor Tr2 is still kept off. The capacitor C is charged by the current originated from the high level comparator signal, allowing the gate potential of the transistor Tr2 to be pulled high. In this situation, when the measuring voltage VE is applied to the measuring terminal 3, the transistors Tr3 and Tr4 turn on. The potential level of the terminal 3 increases up to the measuring voltage VE. As a result, the gate potential of the transistor Tr2 is also raised by a voltage corresponding to measuring voltage VE, and thus becomes higher than the potential level of the power source Vcc. Consequently, the transistor Tr2 is turned on, and current flows from the tester 7 to the power source Vcc through the three transistors Tr4, Tr3 and Tr2. Accordingly, the tester 7 can recognize the coincidence of the input address with the redundant address by detecting the current flowing from the tester 7 into the signature circuit 1.
According to the redundant address detection using the signature circuit as described above, however, the tester 7 is required to increase the potential of the measuring terminal 3 from a low potential level such as a ground level to the measuring voltage VE every time a group of address signals A.sub.0 to A.sub.n is input to the address signal comparator 2. This requires a long testing time to search for the redundant address from a large number of addresses, and consequently results in an increase in testing costs.
In the conventional method, the redundant address is determined by detecting the leakage current from the tester 7 through the signature circuit 1 to the power source Vcc. However, such leakage current is liable to be affected by fluctuation of the measuring voltage VE or by signature circuit transistor dispersion. This reduces the reliability of redundant address detection.